Job opportunities

Post-doctoral positionDesign, characterization and modelling of a random number generator based on oscillating structures in FPGA and ASIC

Duration: 12 months renewable
Start: as soon as possible
Funding: PSPC-regions program funded by the Auvergne Rhône Alpes region

Project outline:
The PSPC-regions project "SECURE-RISC-V" includes 3 partners: two small French companies Tiempo and GreenWaves-Technologies, and the Hubert Curien laboratory in Saint-Etienne.
The objective of the project is to secure microcontrollers targeting IoT applications and based on a RISC-V architecture with an adapted hardware security element.
GreenWaves-Technologies provides a high-performance, low-power multi-core architecture that is secured by the TIEMPO's secure element certifiable CC EAL5+ IP (intellectual property). The Hubert Curien laboratory provides support for the design and stochastic modelling of the random number generator based on asynchronous rings - STR (for Self-timed rings), for the design and verification of stochastic tests dedicated to the generator, as well as for the verification of the generator's security and the efficiency of its dedicated tests.

- Study and modelling of asynchronous rings (STR) as a source of randomness in digital circuits.
- Implementation of random number generators (TRNG) based on these asynchronous rings in FPGA and ASIC circuits.
- Analysis of the statistical properties of the generated numbers.
- Stochastic modelling of the proposed generators.
- Proposal of embedded tests dedicated to the generators, based on their stochastic models.

Candidate profile:
- Ph.D. degree required
- Good knowledge of digital electronics and embedded systems
- CAD tools and FPGA design (Intel, Xilinx or Microsemi) as well as simulation tools (Modelsim)
- ASIC design using Cadence tools (design, simulation, verification)

To apply:
Send Cover letter and CV by e-mail to

Post-doctoral positionSecurity of heterogeneous Systems-on-Chip

Duration: 24 months (possibly renewable)
Start: as soon as possible

Within the framework of a collaborative project funded by the ANR, the Archi-Sec project, the team wishes to strengthen its human potential by hiring a postdoctoral researcher to work on one of its research lines: "Design of trusted embedded systems".
The Archi-Sec project aims to model the architectural problems of SoCs with a virtual platform based on the "gem5" simulation tool. This platform is used for intrusion tests, to evaluate the cost in performances of countermeasures, to anticipate attacks and to propose new protections. The targeted processors are the ARM and RISC-V cores.

Candidate profile
The candidate must hold a PhD and have scientific contributions in at least one of the following fields: hardware security, embedded systems security, heterogeneous SoC design (mixed FPGA / processors), gem5 modelling. The candidate will have to demonstrate his/her ability to be autonomous in carrying out research work and in its valorisation (publication, presentation, etc.).

Candidates should apply by sending a CV and a covering letter to Mr. Lilian Bossuet by e-mail ( as soon as possible.
For further information contact Mr. Lilian Bossuet directly by telephone on (+334 77 91 57 92) or by e-mail (

Job opportunities in the Secure Embedded Systems group

We are always looking for talented researchers. People interested in joining our research group should send a cover letter (motivation letter) and their CV to Viktor Fischer (fischer @ or Lilian Bossuet (lilian.bossuet @

2020-2021 - Doctoral or postdoctoral positions in the fields of:

  • True random number generators
  • Security of heterogeneous system on a chip
  • Secure implementations of code-based schemes

Other opportunities are often available. Do not hesitate to ask.