Unsolicited Applications
We are always looking for talented researchers.
People interested in joining our research group should send a cover letter and their CV to Lilian Bossuet lilian.bossuet @ univ-st-etienne.fr
Doctoral or postdoctoral positions in the fields of:
- True random number generators
- Security of heterogeneous system on a chip
- Secure implementations of code-based schemes
Other opportunities are often available. Do not hesitate to ask.
Ph.D. openings
PH.D. - Caractérisation, modélisation et quantification du bruit de scintillement et son utilisation comme source d’aléa dans les générateurs de nombres aléatoires
Modalités et encadrement
Cette thèse est proposée dans le cadre d’une collaboration entre le Commissariat à l'Énergie Atomique et aux Énergies Alternatives (CEA-Leti à Grenoble) et le Laboratoire Hubert Curien (équipe SESAM : Systèmes Embarqués Sécurisés et Architectures Matérielles).Télécharger le fichier «Sujet_These_UJM_CEA.pdf» (419 Ko)
Ph.D. - Study and design of memory protections for an heterogeneous SoC architecture
Start: 1st september or 1st october 2024
Duration: 36 months
Location: Laboratoire Hubert Curien (Université Jean Monnet - UJM, St-Etienne)
Interested candidates should send a CV and cover letter to both:
- Brice Colombier b.colombier @ univ-st-etienne.fr
- Lilian Bossuet lilian.bossuet @ univ-st-etienne.fr
The objective of this thesis is to investigate potential architectural and micro-architectural attacks targeting the various memories of a heterogeneous SoC architecture (L1, L2, DDR) and to develop countermeasures that can be integrated into its hardware.
For detailed information on the offer, see the page below.
Download the file «PhD_LabHC_SCAMA.pdf» (145.1 Ko)
Postdoc openings
Post-doc - Design, characterization and modelling of a random number generator based on oscillating structures in FPGA and ASIC
Duration: 12 months renewable
Start: as soon as possible
Funding: PSPC-regions program funded by the Auvergne Rhône Alpes regionProject outline:
The PSPC-regions project "SECURE-RISC-V" includes 3 partners: two small French companies Tiempo and GreenWaves-Technologies, and the Hubert Curien laboratory in Saint-Etienne.
The objective of the project is to secure microcontrollers targeting IoT applications and based on a RISC-V architecture with an adapted hardware security element.
GreenWaves-Technologies provides a high-performance, low-power multi-core architecture that is secured by the TIEMPO's secure element certifiable CC EAL5+ IP (intellectual property). The Hubert Curien laboratory provides support for the design and stochastic modelling of the random number generator based on asynchronous rings - STR (for Self-timed rings), for the design and verification of stochastic tests dedicated to the generator, as well as for the verification of the generator's security and the efficiency of its dedicated tests.Missions:
- Study and modelling of asynchronous rings (STR) as a source of randomness in digital circuits.
- Implementation of random number generators (TRNG) based on these asynchronous rings in FPGA and ASIC circuits.
- Analysis of the statistical properties of the generated numbers.
- Stochastic modelling of the proposed generators.
- Proposal of embedded tests dedicated to the generators, based on their stochastic models.Candidate profile:
- Ph.D. degree required
- Good knowledge of digital electronics and embedded systems
- CAD tools and FPGA design (Intel, Xilinx or Microsemi) as well as simulation tools (Modelsim)
- ASIC design using Cadence tools (design, simulation, verification)To apply:
Send Cover letter and CV by e-mail to fischer @ univ-st-etienne.fr